The company is in Xuzhou Economic and technological development zone Phoenix Electronic Information Industry Park, covering an area of about 53 acres, with an investment of nearly 2 billion yuan. The project is divided into two phases. The construction area of the first stage is about 12,000 square meters, including nearly 4,000 square meters of purification production area. After completion, the annual production capacity of 120,000 12-inch wafers will be formed. The total construction area of the second stage project is about 30,000 square meters. The annual production capacity will increase to 1 million 12-inch wafers.
The company's R&D team is composed of internationally renowned enterprises with R&D technology and management experience, leading talents of "mass entrepreneurship and innovation" in Jiangsu Province, and local R&D teams with rich R&D experience. The team members have rich experience in advanced semiconductor packaging field, such as fan-out, fan-in, chip flip, stacked packaging, silicon through-hole and other high-top fields. They have several independent intellectual property rights. As an integrated circuit advanced packaging research and development and production OEM base, Casmeit products/technology is positioned in: Bumping /Micro-Bumping、Wafer Level Chip Scale Packaging (WLCSP)、Fanout Wafer Level Packaging (FOWLP)、3D Packaging & System-in-Packaging, (SIP).
The projects implemented are highly mature since the establishment of the company, and the selection of basic technology and complete process, equipment and materials, etc., are based on the generic technology research and development achievements of the National Science and Technology 02 major project undertaken by China Semiconductor Packaging Pilot R&D Center since 2014. At the present stage, the company's main research and development and production is mainly focusing on wafer-level fan-out packaging technology. With the increasing demand for various big data, wearable, mobile electronic devices and advanced communications, this technology has become the preferred advanced packaging method with its high cost performance advantage. With more than ten independent intellectual property rights, they are advanced customized and reasonable design schemes for different customers. It is a reliable business partner for most customers to apply this technology.
In the future, the company will conduct research and development on the pilot technology of semiconductor sealing and testing. Based on the characteristics of China's integrated circuit and electronic manufacturing industry, we will catch up with international standard and partially surpass the advanced foreign level in the mainstream technology and industrial development, and support the technological upgrading of domestic sealing and testing industry through sustainable development ability and large-scale mass production. We will combine the demands of the upstream and downstream industry chain, and become advanced packaging technology research and development platform, and advanced packaging industrialization base, talent training base, even become one of the world's famous semiconductor sealing and testing enterprises.
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